Electronic components have been continuously designed and fabricated to have a miniaturized profile in response to the progress of integrated circuit (IC) manufacturing technology, and with provision of large-scale and highly integrated electronic circuits, IC-based products have relatively complete functionality.
Conventionally, electronic components are mounted on an electronic carrier board (such as a printed circuit board (PCB), a circuit board, or a substrate) by through hole technology (THT). The electronic components used in the THT, as not able to be further reduced in size, are considered occupying a significant amount of space on the electronic carrier board. By the THT, the electronic carrier board needs to have through holes corresponding to pins of the electronic components, such that the electronic components with the pins coupled to the through holes of the electronic carrier board actually occupy space on both sides of the electronic carrier board, and further, solder joints formed at junctions of the electronic components and the electronic carrier board are relatively large. Due to these drawbacks, the THT is no longer used in the mounting process of electronic components, but instead, surface mounted technology (SMT) becomes widely employed nowadays to effectively mount electronic components on an electronic carrier board.
Using the SMT to mount electronic components, electrical connection ends (pins) of the electronic components are bonded to a surface of an electronic carrier board on which the electronic components are mounted, such that there is no need to form plenty of through holes in the electronic carrier board for accommodating the pins of the electronic components as in the case of using the THT. Further by the SMT, the electronic components can be disposed on both sides of the electronic carrier board, thereby greatly improving space utilization of the electronic carrier board. Compared with the electronic components used in the THT, the electronic components used in the SMT have smaller sizes such that more of these electronic components can be mounted on the electronic carrier board by the SMT, and also, the electronic components used in the SMT are more cost-effectively fabricated. These advantages make the SMT become the main technology for mounting electronic components on an electronic carrier board.
Moreover, in response to the electrical and functional requirements, it becomes necessary to mount passive components (such as capacitors, resistors or inductors) on an electronic carrier board to maintain stable electrical quality of an electronic product.
FIG. 1A is a top view showing passive components mounted on a substrate by the SMT, and FIGS. 1B and 1C are cross-sectional views of FIG. 1A taken along lines 1B-1B and 1C-1C respectively. As shown, a pair of separate bond pads 12 are formed at predetermined positions on a substrate 11, and are exposed through openings 130 of a solder mask layer 13 covering the substrate 11. With an appropriate amount of solder paste 15 being applied on the bond pads 12, two end portions of a passive component 14 can be bonded to the solder paste 15 and then subjected to a reflow soldering process, such that the passive component 14 is electrically connected to the bond pads 12 by means of the solder paste 15. In order to avoid a tombstone effect due to uneven amounts of the solder paste 15 applied to the two end portions of the passive component 14, the openings 130 of the solder mask layer 13 where the pair of bond pads 12 are exposed are made symmetrical in shape and equal in size so as to provide the solder paste 15 with same wetting areas on the bond pads 12.
However, for a semiconductor package, it is found difficult to accurately control the height of the passive component 14 bonded to the solder paste 15 due to the amount of the solder paste 15 being used and melting of the solder paste 15 in the reflow soldering process. In case the solder mask layer 13 does not have a flat surface but is usually formed with recesses, a clearance 17 may be generated between the passive component 14 and the solder mask layer 13. The height of the clearance 17 is merely 10 to 30 μm, which is smaller than the size (about 50 μm) of fillers of an epoxy molding compound (EMC) used for encapsulating the passive component 14. As such, in a molding process, the clearance 17 cannot be completely filled with the EMC, and thus voids are formed. The voids result in a popcorn effect in a subsequent high-temperature operating environment, which undesirably damages the whole package structure. Furthermore, the melting solder paste 15 may flow into the clearance 17 (by a capillary action) and lead to undesirable electrical bridging and short circuit of the passive component 14 (as shown in FIG. 1B), thereby adversely affecting the yield of the fabricated package structure.
With a plurality of passive components 14 being provided, the melting solder paste 15 may possibly flow through any gap between the bond pads 12 and the solder mask layer 13 and then through any gap between the substrate 11 and the solder mask layer 13 to form solder extrusion (as indicated by the sign SE in FIG. 1C), which results in short circuit between the adjacent passive components 14.
Accordingly, U.S. Pat. No. 6,521,997 provides a solution by additionally forming a groove 230 in a solder mask layer 23 and between openings of the solder mask layer 23 where a pair of bond pads 22 are exposed, as shown in FIG. 2A, so as to enlarge the clearance to allow the EMC to pass through the clearance by means of the groove 230.
However, the size of the groove 230 is limited by the low resolution of the photosensitive solder mask layer 23, such that the smallest width of the groove that can be formed is 150 μm. Moreover, owing to the limitation in photomask alignment precision of the openings through which the bond pads are exposed, the minimum width M of the solder mask layer formed at an edge of each bond pad and around the corresponding opening is 75 μm. This thereby makes it more difficult to form the groove between the bond pads when the component size is being reduced.
The dimensions (e.g. length and width) of a passive component are currently presented by two 2-digit numbers in the semiconductor industry, for example, 0603-type or 0402-type passive component, wherein both the length and width are typically measured in British unit (such as inch), and generally the first 2-digit number presents the larger dimension (i.e. length) followed by the second 2-digit number representing the smaller dimension (i.e. width). Taking the 0402-type passive component as an example, 0402 means the passive component having specific dimensions of 0.040 inch (length)×0.020 inch (width), which if being converted into SI unit, correspond to a length of 0.040×25.4=1.016 mm (approximately 1000 μm) and a width of 0.020×25.4=0.508 mm (approximately 500 μm). The 0402-type passive component usually has a height of 500 μm, which can be a chip capacitor, resistor or inductor.
As shown in FIG. 2B, since semiconductor devices are being made with light weight and compact profile, a thin and fine ball grid array (TFBGA) semiconductor package has been downsized to have the thickness of an encapsulant reduced to 530 μm. Thus, the 0402-type chip passive component having a height of 500 μm becomes unable to be accommodated in such thin semiconductor package, but a smaller 0201-type chip passive component should be used instead so as to reduce the overall thickness of the package structure. The length, width and height of the 0201-type chip passive component are half of those of the 0402-type chip passive component, that is, the 0201-type chip passive component is of 500 μm (length)×250 μm (width)×250 μm (height). In light of the length (500 μm) of the small 0201-type chip passive component, spacing (A1) between two paired bond pads on a substrate has to be decreased from 400 μm to 275 μm.
As described above, the solder mask layer is typically made of a photosensitive material, and due to the low photosensitive resolution and the limitation in photomask alignment precision of openings, the solder mask layer formed at the edge of each bond pad and around the corresponding opening must be at least 75 μm wide. If the technology disclosed in U.S. Pat. No. 6,521,997 of forming a 150 μm-wide groove in the solder mask layers and between the paired bond pads is applied, as shown in FIG. 2B, the width A2 of the solder mask layer formed at the edge of each bond pad and around the corresponding opening becomes merely (275-150)/2=62.5 μm, which is smaller than the minimum width of 75 μm as required and thus goes beyond the capability of current technology.
Alternatively, as shown in FIG. 3A, U.S. Published Application No. 2005/0253231 discloses forming two solder mask openings 330 that expose corresponding sidewalls of two paired bond pads 32, and providing a barrier 331 between the two openings 330, such that two grooves 3300 are formed and allow the EMC to pass therethrough.
However, as limited by the low resolution of the photosensitive solder mask layer, the above technology is not feasible for forming the barrier 331 in the case of the spacing between adjacent bond pads being smaller than 275 μm, and thus is not applicable to the 0201-type passive component.
Further, if there is shifting of the solder mask layer, it would cause unequal wetting areas of the two bond pads in the above technology. As shown in FIG. 3B, assuming that an original bonding area of a bond pad (i.e. a surface area of a bond pad exposed through a solder mask opening) is sized A×B, if the solder mask layer is shifted to the left by X μm (the maximum shift is 75 μm for a conventional substrate fabrication process), the bonding area of the left bond pad becomes B×(A+X) and the bonding area of the right bond pad becomes B×(A−X), resulting in a difference of bonding area of B×(A+X)−B×(A−X)=2BX between the left bond pad and the right bond pad. The different bonding areas cause unequal wetting areas for the solder paste bonded to the bonds pads and lead to the tombstone effect as previously discussed.
Moreover, neither U.S. Pat. No. 6,521,997 nor U.S. Published Application No. 2005/0253231 as mentioned above is able to effectively solve the problem of short circuit between adjacent passive components due to solder extrusion formed by the solder paste flowing through any gap between the substrate and the solder mask layer.
Therefore, the problem to be solved here is to provide an electronic carrier board, which can avoid formation of voids, electrical bridging and solder extrusion in the presence of a clearance formed between the electronic carrier board and an electronic component mounted thereon, as well as prevent unequal exposed bonding areas of bond pads and the tombstone effect due to shifting of solder mask openings through which the bond pads are exposed.